library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.Estructuras_de_Datos.all;
entity Voltimetro is
port ( clock: in std_logic;
d : in std_logic;
not_q: out std_logic;
hs,vs: out std_logic;
r,g,b: out std_logic
);
end entity;
architecture arc1 of Voltimetro is
component Contador_Principal is
port ( clock : in std_logic;
q_ffd: in std_logic;
reset: in std_logic;
salida: out num_BCD(2 downto 0)
);
end component;
component Sigma_Delta is
port(
clock: in std_logic;
d: in std_logic;
n_q: out std_logic;
q: out std_logic
);
end component;
component Decodificador_BCD is
port (
num1,num2,num3 : in std_logic_vector(3 downto 0);
c_1,c_2,c_3:out std_logic_vector(5 downto 0)
);
end component;
component Controlador_VGA is
generic (N:integer:=10);
port ( clock: in std_logic;
c_1,c_2,c_3: in std_logic_vector(5 downto 0);
hs: out std_logic;
vs: out std_logic;
rojo_out: out std_logic;
verde_out: out std_logic;
azul_out: out std_logic
);
end component;
signal q_ff: std_logic;
signal rst:std_logic:='0';
signal BCDs:num_BCD(2 downto 0);
signal c1,c2,c3:std_logic_vector (5 downto 0);
begin
sd: Sigma_Delta port map(clock,d,not_q,q_ff);
cp: Contador_Principal port map(clock,q_ff,rst,BCDs);
dBcd:Decodificador_BCD port map(BCDs(2),BCDs(1),BCDs(0),c1,c2,c3);
cvga: Controlador_VGA port map (clock,c1,c2,c3,hs,vs,r,g,b);
end;
************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package Estructuras_de_Datos is
type num_BCD is array (natural range <>) of std_logic_vector(3 downto 0);
subtype ciclos_clock is integer range 0 to 1000000000;
function decBCD(a:std_logic_vector(3 downto 0)) return std_logic_vector;
end;
package body Estructuras_de_Datos is
function decBCD(a:std_logic_vector(3 downto 0)) return std_logic_vector is
variable resultado: std_logic_vector(5 downto 0):=(others=>'0');
begin
case a is
when "0001" =>
resultado := "001101";
when "0010" =>
resultado := "001110";
when "0011" =>
resultado := "001111";
when "0100" =>
resultado := "010000";
when "0101" =>
resultado := "010001";
when "0110" =>
resultado := "010010";
when "0111" =>
resultado := "010011";
when "1000" =>
resultado := "010100";
when "1001" =>
resultado := "010101";
when "0000" =>
resultado := "010110";
when others =>
resultado := "XXXXXX";
end case;
return resultado;
end function;
end;
***************************************************************************************
--------------------------------------------------
--Contador que que utiliza cuatro contadores de 4 bits
-- y determina la logica de la misma
--------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.Estructuras_de_Datos.all;
entity Contador_BCD is
generic (n:integer);
port ( clock: in std_logic;
reset: in std_logic;
enabled: in std_logic;
out_con: out num_BCD(n-1 downto 0)
);
end;
--vectores_salida cambiado por num_BCD
architecture arc1 of Contador_BCD is
component Contador_4_bits is
port ( clock : in std_logic;
reset: in std_logic;
enabled: in std_logic;
q:out std_logic_vector(3 downto 0)
);
end component;
--signal q_con: num_BCD(3 downto 0);
--signal rsts:std_logic_vector(3 downto 0):="0000";
--signal enabs: std_logic_vector(3 downto 0):="0000";
--signal carry:std_logic_vector(2 downto 0):="000";
signal q_con: num_BCD(n-1 downto 0);
signal rsts:std_logic_vector(n-1 downto 0):=(others=>'0');
signal enabs: std_logic_vector(n-1 downto 0):=(others=>'0');
signal carry:std_logic_vector(n-2 downto 0):=(others=>'0');
begin
--genCon: for i in 3 downto 0 generate
genCon:
for i in 0 to n-1 generate
con: Contador_4_bits port map (clock,rsts(i),enabs(i),q_con(i));
out_con (i)(3 downto 0)<=q_con (i)(3 downto 0);
end generate;
genEnabs:
for i in 1 to n-1 generate
enabs(i)<=(((enabs(i-1) and carry(i-1)) or reset) and enabled) or rsts(i);
end generate;
enabs(0)<=enabled or rsts(0);
process (clock)
begin
-- for i in 0 to 2 loop
for i in 0 to n-2 loop
if q_con(i)="1001" or q_con(i)="1010" then
carry(i)<='1';
else
carry(i)<='0';
end if;
end loop;
-- if reset='1' and enabled='1' then
-- rsts(3 downto 0)<="1111";
-- elsif reset='0' then
-- rsts(3 downto 0)<="0000";
-- end if;
if reset='1' then --and enabled='1' then
rsts(n-1 downto 0)<=(others=>'1');
elsif reset='0' then
rsts(n-1 downto 0)<=(others=>'0');
end if;
--for i in 0 to 3 loop
for i in 0 to n-1 loop
if q_con(i)="1010" then
rsts(i)<='1';
end if;
end loop;
end process;
--out_con (3 downto 0)(3 downto 0)<=q_con (3 downto 0)(3 downto 0);
-- out_con (3)(3 downto 0)<=q_con (3)(3 downto 0);
-- out_con (2)(3 downto 0)<=q_con (2)(3 downto 0);
-- out_con (1)(3 downto 0)<=q_con (1)(3 downto 0);
-- out_con (0)(3 downto 0)<=q_con (0)(3 downto 0);
-- GenSalidas: for i in 0 to n-1 generate
-- out_con (i)(3 downto 0)<=q_con (i)(3 downto 0);
-- end generate;
--enabs(0)<=enabled or rsts(0);
-- enabs(1)<=(((enabs(0) and carry(0)) or reset) and enabled)or rsts(1);
-- enabs(2)<=(((enabs(1) and carry(1)) or reset) and enabled) or rsts(2);
-- enabs(3)<=(((enabs(2) and carry(2)) or reset) and enabled) or rsts(3);
-- GenEnab: for i in 1 to n-1 generate
-- enabs(i)<=(((enabs(i-1) and carry(i-1)) or reset) and enabled) or rsts(i);
-- end generate;
end;
***************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Controlador_VGA is
generic (N:integer:=10);
port (
clock: in std_logic;
c_1,c_2,c_3: in std_logic_vector(5 downto 0);
hs: out std_logic;
vs: out std_logic;
rojo_out: out std_logic;
verde_out: out std_logic;
azul_out: out std_logic
--pixel_col : out std_logic_vector (N-1 downto 0);
--pixel_fila:out std_logic_vector(N-1 downto 0);
);
end entity;
architecture arc1 of Controlador_VGA is
component Char_ROM is
generic(
N: integer:= 6;
M: integer:= 3;
W: integer:= 8
);
port(
char_address: in std_logic_vector(5 downto 0);
font_row, font_col: in std_logic_vector(M-1 downto 0);
rom_out: out std_logic
);
end component;
component vgadrive is
port( clock : in std_logic; -- 25.175 Mhz clock
red, green, blue : in std_logic; -- input values for RGB signals
row, column : out std_logic_vector(9 downto 0); -- for current pixel
Rout, Gout, Bout, H, V : out std_logic); -- VGA drive signals
end component;
constant pos_char_fila:integer:=58;
constant pos_char_col:integer:=50;
constant col_1er_char:integer:=pos_char_col;
constant col_2do_char:integer:=pos_char_col+12;
constant col_3er_char:integer:=pos_char_col+24;
constant col_4to_char:integer:=pos_char_col+36;
constant col_5to_char:integer:=pos_char_col+48;
signal col_rel,col,fila_rel,fila:std_logic_vector(N-1 downto 0);
signal h_sync,v_sync:std_logic;
signal clock_div:std_logic:='0';
signal rojo_in,verde_in,azul_in:std_logic;
signal dir_char_actual:std_logic_vector(5 downto 0);
constant dir_char_punto:std_logic_vector(5 downto 0) :="001011";--SETEAR LA DIRECCION CORRECTA!!!!!!!!!!!!!! ES 22
constant dir_char_unidad:std_logic_vector(5 downto 0):="001100";--SETEAR LA DIRECCION CORRECTA!!!!!!!!!!!!!! ES 24
signal font_col,font_fila:std_logic_vector(2 downto 0):=(others=>'0');
signal pixel_rom:std_logic;
signal pintar_pixel:std_logic;
signal habilitado_pintar:std_logic;
begin
bb: char_rom port map(dir_char_actual, font_fila,font_col,pixel_rom);
aa: vgadrive port map( clock_div,rojo_in,verde_in,azul_in,
fila,col,
rojo_out,verde_out,azul_out,
h_sync,v_sync);
hs <= h_sync;
vs <= v_sync;
col_rel(N-1 downto 0) <= "00"&col(N-1 downto 2);
fila_rel(N-1 downto 0) <= "00"&fila(N-1 downto 2);
process(clock)
begin
if rising_edge(clock) then
clock_div <= not clock_div;
end if;
end process;
pintar_pixel <= pixel_rom and habilitado_pintar;
process(pintar_pixel)
begin
rojo_in <= pintar_pixel;
verde_in <= pintar_pixel;
azul_in <= pintar_pixel;
end process;
process (col_rel,fila_rel)
variable Vfont_col,Vfont_fila:std_logic_vector(N-1 downto 0);
begin
if fila_rel >= pos_char_fila and fila_rel <= pos_char_fila+8 then
if col_rel >= col_1er_char and col_rel < col_1er_char+8 then
dir_char_actual <= c_1;
habilitado_pintar<= '1';
Vfont_col := col_rel - col_1er_char;
elsif col_rel >= col_2do_char and col_rel < col_2do_char+8 then
dir_char_actual <= dir_char_punto;
habilitado_pintar<= '1';
Vfont_col := col_rel - col_2do_char;
elsif col_rel >= col_3er_char and col_rel < col_3er_char+8 then
dir_char_actual <= c_2;
habilitado_pintar<= '1';
Vfont_col := col_rel - col_3er_char;
elsif col_rel >= col_4to_char and col_rel < col_4to_char+8 then
dir_char_actual <= c_3;
habilitado_pintar<= '1';
Vfont_col := col_rel - col_4to_char;
elsif col_rel >= col_5to_char and col_rel < col_5to_char+8 then
dir_char_actual <= dir_char_unidad;
habilitado_pintar<= '1';
Vfont_col := col_rel - col_5to_char;
else
habilitado_pintar <= '0';
Vfont_col := (others=>'0');
end if;
Vfont_fila := fila_rel - pos_char_fila;
font_fila <= Vfont_fila(2 downto 0);
font_col <= Vfont_col(2 downto 0);
else
habilitado_pintar <= '0';
end if;
end process;
end;
******************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity Sigma_Delta is
port(
clock: in std_logic;
d: in std_logic;
n_q: out std_logic;
q: out std_logic
);
end entity;
architecture arc1 of Sigma_Delta is
component ffd_sd is
port ( d: in std_logic;
enb: in std_logic;
rst: in std_logic;
q: out std_logic
);
end component;
signal rst:std_logic:='0';
signal enb:std_logic:='0';
signal q_ff:std_logic:='0';
begin
q <= q_ff;
n_q <= not q_ff;
rst<='0';
ff : ffd_sd port map(d,clock,rst,q_ff);
end;
***************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.Estructuras_de_Datos.all;
entity Decodificador_BCD is
port (
num1,num2,num3 : in std_logic_vector(3 downto 0);
c_1,c_2,c_3:out std_logic_vector(5 downto 0)
);
end entity;
architecture arc1 of Decodificador_BCD is
begin
c_1 <= decBCD (num1);
c_2 <= decBCD (num2);
c_3 <= decBCD (num3);
end;
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