library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Multiplexor is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; sel : in STD_LOGIC_VECTOR (1 downto 0); x : inout STD_LOGIC); end Multiplexor; architecture Behavioral of Multiplexor is signal g:std_logic; begin process (a,b,c,d,sel) begin if sel = "00" then x<=a; elsif sel = "01" then x<=b; elsif sel = "10" then x<=c; else x<=d; end if; end process; end Behavioral;