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Multiplexor ( codigo ) vhdl

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Multiplexor is     Port ( a : in  STD_LOGIC;            b : in  STD_LOGIC;            c : in  STD_LOGIC;            d : in  STD_LOGIC;            sel : in  STD_LOGIC_VECTOR (1 downto 0);            x : inout  STD_LOGIC); end Multiplexor; architecture Behavioral of Multiplexor is signal g:std_logic; begin process (a,b,c,d,sel) begin if sel = "00" then x<=a; elsif sel = "01" then x<=b; elsif sel = "10" then x<=c; else x<=d; end if; end process; end Behavioral;

ALU ( arithmetic logic unit ) vhdl codigo

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity operaciones is port( clk: in std_logic; switch1,switch2,push1,push2: inout std_logic; display: out std_logic_vector (7 downto 0):="00000000"; leds, anodos: out std_logic_vector (3 downto 0):="0000"); end operaciones; architecture Behavioral of operaciones is signal barrido,bleds,modo: std_logic_vector (1 downto 0):="00"; signal break,break2: std_logic :='0'; signal mode,anod: std_logic_vector (3 downto 0):="0000"; signal contador: std_logic_vector (9 downto 0):="0000000000"; signal disp,disp1,disp2,disp3: std_logic_vector (7 downto 0):="00000010"; signal x,y,z,w: std_logic_vector (3 downto 0):="0000"; signal x2,y2,z2,w2: std_logic_vector (3 downto 0):="0000"; signal matr: std_logic_vector (3 downto 0):="0000"; signal dispa,disp1a,disp2a,disp3...