library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity cronometro is Port ( display : out STD_LOGIC_VECTOR (7 downto 0); clk, reset, enc : in STD_LOGIC; An : out STD_LOGIC_VECTOR (3 downto 0)); end cronometro; architecture Behavioral of cronometro is signal contador: std_logic_vector (3 downto 0) :="0000"; signal segundos: std_logic_vector (13 downto 0) :="00000000000000"; signal contador1: std_logic_vector (3 downto 0) :="0000"; signal DecSeg: std_logic_vector (9 downto 0) :="0000000000"; signal contador2: std_logic_vector (3 downto 0) :="0000"; signal CentSeg: std_logic_vector (7 downto 0) :="00000000"; signal Anodos: std_logic_vector (1 downto 0 ):="00"; begin Process (clk, reset, contador, segundos) begin if (clk'event and clk = '1') then ...