library IEEE; use IEEE.std_logic_1164.all; library work; use work.Estructuras_de_Datos.all; entity Voltimetro is port ( clock: in std_logic; d : in std_logic; not_q: out std_logic; hs,vs: out std_logic; r,g,b: out std_logic ); end entity; architecture arc1 of Voltimetro is component Contador_Principal is port ( clock : in std_logic; q_ffd: in std_logic; reset: in std_logic; salida: out num_BCD(2 downto 0) ); end component; component Sigma_Delta is port( clock: in std_logic; d: in std_logic; n_q: out std_logic;